FIG. 1 shows a prior art static read/write memory cell 10 such as is typically used in high-density static random access memories (SRAMs). A static memory cell is characterized by operation in one of two mutually-exclusive and self-maintaining operating states. Each operating state defines one of the two possible binary bit values, zero or one. A static memory cell typically has an output which reflects the operating state of the memory cell. Such an output produces a "high" voltage to indicate a "set" operating state. The memory cell output produces a "low" voltage to indicate a "reset" operating state. A low or reset output voltage usually represents a binary value of zero, while a high or set output voltage represents a binary value of one.
A static memory cell is said to be bistable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable output voltage, corresponding to the operating state of the memory cell, as long as the memory cell receives power.
The two possible output voltages produced by a static memory cell correspond generally to upper and lower circuit supply voltages. Intermediate output voltages, between the upper and lower circuit supply voltages, generally do not occur except for during brief periods of memory cell power-up and during transitions from one operating state to the other operating state.
The operation of a static memory cell is in contrast to other types of memory cells such as dynamic cells which do not have stable operating states. A dynamic memory cell can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or "refreshing" to maintain this voltage for more than very short time periods.
A dynamic memory cell has no internal feedback to maintain a stable output voltage. Without refreshing, the output of a dynamic memory cell will drift toward intermediate or indeterminate voltages, resulting in loss of data. Dynamic memory cells are used in spite of this limitation because of the significantly greater packaging densities which can be attained. For instance, a dynamic memory cell can be fabricated with a single MOSFET transistor, rather than the six transistors typically required in a static memory cell. Because of the significantly different architectural arrangements and functional requirements of static and dynamic memory cells and circuits, static memory design has developed along generally different paths than has the design of dynamic memories.
Static memory cell 10 generally comprises first and second inverters 12 and 14 which are cross-coupled to form a bistable flip-flop. Inverters 12 and 14 are formed by n-channel driver transistors 16 and 17, and p-channel load transistors 18 and 19. Driver transistors 16 and 17 are typically metal oxide silicon field effect transistors (MOSFETs) formed in an underlying silicon semiconductor substrate. P-channel transistors 18 and 19 are typically thin film transistors formed above the driver transistors.
The source regions of driver transistors 16 and 17 are tied to a low reference or circuit supply voltage, labelled V.sub.ss and typically referred to as "ground." Load transistors 18 and 19 are connected in series between a high reference or circuit supply voltage, labelled V.sub.cc, and the drains of the corresponding driver transistors 16 and 17. The gates of load transistors 18 and 19 are connected to the gates of the corresponding driver transistors 16 and 17.
Inverter 12 has an inverter output 20 formed by the drain of driver transistor 16. Similarly, inverter 14 has .an inverter output 22 formed by the drain of driver transistor 17. Inverter 12 has an inverter input 24 formed by the gate of driver transistor 16. Inverter 14 has an inverter input 26 formed by the gate of driver transistor 17.
The inputs and outputs of inverters 12 and 14 are cross-coupled to form a flip-flop having a pair of complementary two-state outputs. Specifically, inverter output 20 is cross-coupled to inverter input 26, and inverter output 22 is cross-coupled to inverter input 24. In this configuration, inverter outputs 20 and 22 form the complementary two-state outputs of the flip-flop.
A memory flip-flop such as that described typically forms one memory element of an integrated array of static memory elements. A plurality of access transistors, such as access transistors 30 and 32, are used to selectively address and access individual memory elements within the array. Access transistor 30 is an n-channel MOSFET having one active terminal connected to cross-coupled inverter output 20. Access transistor 32 is an n-channel MOSFET having one active terminal connected to cross-coupled inverter output 22. A plurality of complementary column line pairs, such as the single pair of complementary column lines 34 and 36 shown, are connected to the remaining active terminals of access transistors 30 and 32, respectively. A row line 38 is connected to the gates of access transistors 30 and 32.
Reading static memory cell 10 requires activating row line 38 to connect inverter outputs 20 and 22 to column lines 34 and 36. Writing to static memory cell 10 requires first placing selected complementary logic voltages on column lines 34 and 36, and then activating row line 38 to connect those logic voltages to inverter outputs 20 and 22. This forces the outputs to the selected logic voltages, which will be maintained as long as power is supplied to the memory cell, or until the memory cell is reprogrammed.
It is an accepted fact that most types of electronic read/write memories, including SRAMs, do not retain their programmed information without power being supplied. Even so-called "non-volatile" read/write memories retain their programming only because they include internal batteries. The batteries provide a rechargeable internal power source which is activated in the absence of external power.
In the specific case of static memory cells such as memory cell 10 described above, removing power causes a permanent loss of the binary information which had previously been stored. Upon subsequent power-up, numerous arbitrary and variable factors, such as the comparative capacitance and resistance associated with each of the inverters and their associated cross-couplings, determine whether an individual memory cell .will begin operation in one state or the other. Thus, a memory array contains only random information upon power-up, and cannot be guaranteed to contain any information with which it had been programmed before power was removed.
The need for non-volatile storage is apparent from the popularity of battery-backed static memories. However, a non-volatile memory without associated backup batteries is needed and, if available, would find application in a great variety of products. The invention described below meets this need within a static memory array.